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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:22:35 04/25/2012 
-- Design Name: 
-- Module Name:    counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
	Port (
			clk : in std_logic;
			update_pulse : in std_logic;
			count : out std_logic_vector(1 downto 0)
		);
end counter;

architecture Behavioral of counter is
	signal count_current : std_logic_vector(1 downto 0) := "00";
	signal count_next : std_logic_vector(1 downto 0);
begin

	process(clk)
	begin
		if rising_edge(clk) then
			count_current <= count_next;
		end if;
	end process;
	
	with update_pulse select count_next <=
		std_logic_vector( unsigned(count_current) + 1 ) when '1',
		count_current when others;
		
	count <= count_current;

end Behavioral;

